1. Technical Field
The invention relates generally to a method of power supply noise and signal integrity analysis for creating frequency-dependent electrical models, and is particularly related to power supply and signal integrity analysis of microelectronic package structures.
2. Related Art
A long-standing problem in the design of semiconductor integrated circuit chip systems has been the proper assessment of signal integrity, coupling, power supply noise, and resonances such as LC resonance, and package cavity resonance. Accurately modeling these electrical phenomena is made difficult by the large number of system components—typically at least thousands of vias, hundreds of signal wires, multiple power supplies, and complicated power-plane structures. As used throughout this specification, the term “vias” is intended to denote vertical, electrically conductive connections between different electrically conductive planes or signal lines, where these vertical connections are perpendicular to the planes and the signal lines. The problem is compounded at higher frequencies (i.e., frequency ranges above approximately 1 GHz), where the electromagnetic flight time across the system is longer than the switching time of the signals. Transmission line effects become dominant, and any accurate model must take the propagation delays through the structure into account.
In the past, a popular technique for modeling system components has been to calculate their electrical interaction as if there were no time delay between them. This so-called “lumped element” approach works at low frequencies (e.g., up to about 100 MHz), but yields results that are significantly erroneous at the higher frequencies commonly used today. With this lumped element technique, all components are assumed to interact with all other components. A network of inductors (L), resistors (R), and capacitors (C), is used to create a circuit model which represents the electrical interactions of the system's components. This RLC network is then simulated with a circuit-solver program such as SPICE. This technique creates an electrical representation of a microelectronic package, chip, or board in a readily portable and simulatable, industry-standard format. However, errors arise with this technique when the rise time of the signals is faster than the interaction of the system's components, which is limited by the speed of light in the medium.
Another characteristic of common simulation methodologies is that these full-wave electromagnetic simulation methods use the entire geometry of the system in an attempt to model all the wires simultaneously. Such simulation models, whether two-dimensional or three-dimensional, attempt to simulate conditions wherein each wire couples to every other wire. Given a number of signal wires equal to N, the resultant simulation produces an (N×N) matrix, which in turn produces an N-squared computational problem. As N becomes large, the computations become prohibitively slow.
Thus, a need exists for a method of creating, from the component geometries of a system in a manner that takes into account the switching time of the signals and the time delay between the components, circuit models that will run efficiently on familiar circuit simulators, and which overcome the deficiencies of the related art.